FZGPUModules 2.0
GPU-accelerated modular compression pipelines
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PtxUtils.h
1
9#ifndef FZ_ANS_DIETGPU_UTILS_PTXUTILS_H
10#define FZ_ANS_DIETGPU_UTILS_PTXUTILS_H
11
12#pragma once
13
14#include <cuda.h>
15
16namespace fz { namespace ans {
17
18__device__ __forceinline__ int getLaneId() {
19 int laneId;
20 asm("mov.u32 %0, %%laneid;" : "=r"(laneId));
21 return laneId;
22}
23
24__device__ __forceinline__ unsigned getLaneMaskLt() {
25 unsigned mask;
26 asm("mov.u32 %0, %%lanemask_lt;" : "=r"(mask));
27 return mask;
28}
29
30__device__ __forceinline__ unsigned getLaneMaskLe() {
31 unsigned mask;
32 asm("mov.u32 %0, %%lanemask_le;" : "=r"(mask));
33 return mask;
34}
35
36__device__ __forceinline__ unsigned getLaneMaskGt() {
37 unsigned mask;
38 asm("mov.u32 %0, %%lanemask_gt;" : "=r"(mask));
39 return mask;
40}
41
42__device__ __forceinline__ unsigned getLaneMaskGe() {
43 unsigned mask;
44 asm("mov.u32 %0, %%lanemask_ge;" : "=r"(mask));
45 return mask;
46}
47
48template <typename T, int Width = kWarpSize>
49__device__ inline T warpReduceAllSum(T val) {
50#if __CUDA_ARCH__ >= 800
51 return __reduce_add_sync(0xffffffff, val);
52#else
53#pragma unroll
54 for (int mask = Width / 2; mask > 0; mask >>= 1) {
55 val += __shfl_xor_sync(0xffffffff, val, mask, kWarpSize);
56 }
57
58 return val;
59#endif
60}
61
62}} // namespace fz::ans
63
64#endif // FZ_ANS_DIETGPU_UTILS_PTXUTILS_H
Definition dag.h:24