FZGPUModules 2.0
GPU-accelerated modular compression pipelines
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warp_op_params.h File Reference

POD parameter blocks for the warp-register predictor policies. More...

#include <cstdint>

Go to the source code of this file.

Classes

struct  fz::fused::warp::Lorenzo1DParams
 
struct  fz::fused::warp::TiledLorenzo2DParams
 cuSZp3: linear-ABS quant + 2-D separable tiled Lorenzo (tz == 1). More...
 
struct  fz::fused::warp::TiledLorenzo3DParams
 cuSZp3: linear-ABS quant + 3-D separable tiled Lorenzo (tz > 1). PROTOTYPE. More...
 

Namespaces

namespace  fz
 

Variables

constexpr uint32_t fz::fused::warp::kMaxWarpElemsPerLane = 4
 

Detailed Description

POD parameter blocks for the warp-register predictor policies.

Shared VERBATIM between the device policies (warp_fusion.cuh, which using these) and the host predictor stages that pack these bytes into the fused params blob (which the generated kernel reinterpret_casts). Keep them plain POD and dependency-free (no device code), so both the host stage compile (g++) and the device compile (nvcc / NVRTC) agree on the layout — the LC-of chunk_op_params.h.

CONVENTION: every warp predictor's Params begins with float inv2eb at offset 0. The predictor stage cannot know the error bound (the quantizer owns it), so it packs 0 there; the generic runner overwrites those 4 bytes with 1/(2*abs_eb) resolved from the primed quantizer bound before uploading the blob.

Variable Documentation

◆ kMaxWarpElemsPerLane

constexpr uint32_t fz::fused::warp::kMaxWarpElemsPerLane = 4
constexpr

Largest block a warp-register fused kernel accepts, in elements-per-lane (block_size = 32 * EPL). Shared by the predictor + coder stages (which gate their fused-op declarations on it) and the launcher (which forces the two-pass path for EPL > 2 — the single-pass body holds BlocksPerWarp*EPL deltas in local memory).

Set to 4 (block 128) by measurement: on CLDHGH 3600x1800 / H100 / eb 1e-3 the fused Quantizer->Lorenzo(1-D)->AdaptiveBitpack compress throughput climbs 201 (EPL 1) -> 245 (2) -> 255 (3) -> 275 (4) GB/s and then PLATEAUS (~266-271 GB/s for EPL 5-8) while per-lane register/local-memory pressure keeps rising. EPL 4 also covers every natural block size (32 = cuSZp2, 64 = cuSZp3 / 1-D, 128 = SZp). Bump only with a measured throughput win.